A field effect transistor with buried channel is known from U.S. Pat. No. 4,984,036. This transistor comprises an active layer formed on a substrate and a buried channel constituted by recesses arranged at three levels in the active layer. Each buried channel recess in this transistor is formed so as to be narrower and deeper at each subsequent level as the channel approaches the substrate. This transistor also comprises a gate electrode which is arranged so as to be in contact with the active layer in the central recess of the channel closest to the substrate.
This gate electrode is formed so as to be than the central recess of the channel in which it is provided. The field effect transistor thus formed may have a high electron mobility in that the active layer is constituted by two layers of material having different electron affinity so that they form a heterojunction. The field effect transistor may be realized in a Ill-V semiconductor material system with a substrate made of GaAs.
The process of manufacturing the known transistor comprises the steps of forming the active layer on a substrate, forming the recesses for the buried channel at different levels, and depositing the gate metallization in the narrowest, deepest recess.
The steps for forming the recesses comprise: depositing a protective layer of dielectric material (SiN or SiO.sub.2), depositing a photoresist layer, providing an opening in the photoresist layer having a width which is exactly equal to that of the future gate metallization of the transistor, selectively etching the subjacent protective layer and the active layer to form second and third openings having widths equal to the opening in the photoresist, enlarging the second opening in the protective layer by selective etching, by under-etching said protective layer with respect to the photoresist opening, and selectively etching the active layer, resulting in under-etching the active layer with respect to the protective layer and a narrower and deeper central recess.
At this stage of the known process, the transistor presents a two-stage gate recess. According to this known process, the resulting transistor comprises a greater number of recesses which one formed by repeating the last two steps. The next process step comprises the deposition of the gate metallization through the photoresist opening, which is still the same as at the beginning of the process, thus providing a gate electrode contact which is narrower than the deepest recess.
This process finally comprises the steps of realizing source and drain electrodes by providing a last protecting layer covering the recesses and the gate electrode, forming openings in said last protecting layer and depositing the source and drain metallizations in said openings of the last protecting layer.
Said multi-step etching process to which the active layer is subjected gradually increases the recess width of the deepest part of said recess. But due to selective etching, the width of the first opening in the resist is never enlarged. Thus, finally the width of the deepest part of the recess formed by said multiple etching process exceeds the width of the photoresist aperture. This is the reason why the gate electrode contact, which has the same width as the photoresist aperture, is narrower than the deepest recess.
The technical problem resolved by this known transistor results in any improvement of the breakdown voltage without an increase in gate-source resistance.
Several field effect transistor types are currently being used, among them transistors which are normally conducting (N-ON) when the gate is at the same potential as the source and which are pinched off through depletion when the potential of the gate is more negative than that of the source, and transistors which are normally pinched off (N-OFF) when the gate is at the same potential as the source and which are rendered conducting by enhancement when the potential of the gate becomes more positive than that of the source.
In the depletion-type and enhancement-type field effect transistors, the active layer below the gate electrode has a given thickness, more particularly a thickness which is smaller in the enhancement-type transistor than in the depletion-type transistor. It is often advantageous to realize amplifier transistors by means of enhancement-type transistors, while the charges are realized in active form by depletion-type transistors in integrated semiconductor devices made from III-V materials, such as GaAs compounds in a favorable case.
In vacuum or air, for example, the doped GaAs material of the active layer normally has a surface tension which is determined by the Fermi-level--the surface states being situated in the center of the forbidden band--which is of the order of -0.5 V. As a result, the active layer is normally depleted on either side of the gate contact, in the so-called access zones, which are, accordingly, non-conducting in the normal state.
In the depletion-type transistor, this surface effect is less unfavorable only if the active layer is comparatively thick below the gate, which allows the transistor to be normally conducting up to the moment when of a negative gate voltage application depletes the active layer also below the gate itself, rendering the transistor completely non-conducting.
In the enhancement-type transistor (N-OFF), where the active layer below the gate is thinner, this surface effect is always very unfavorable because the depleted access regions occupy non-negligible portions of the active layer with respect to the thickness on either side of the gate. These depleted access regions are not rendered conducting by the application of a positive gate voltage with respect to the source, so that the active layer is increased practically only below the gate, and accordingly the number of electrons generated is lower than expected. In addition, the saturation velocity is reduced. Accordingly, the saturation current, which depends on the number of generated electrons and on the saturation velocity, is reduced thereby.
A solution to the problem posed by these depleted access regions, especially in the case of enhancement-type transistors (N-OFF), is achieved by embodying these transistors so as to have very narrow access regions, for example of the order of magnitude of the channel width. This solution is not of practical use in the industry. In fact, the realization of transistors having extremely small access regions requires the implementation of specific techniques, which are very costly, difficult to carry out, and thus only suitable for small batches of manufactured circuits, i.e unfavorable for industrial development.